esmt preliminary AD82581B elite semiconductor memory technology inc. publication date: dec. 2008 revision: 0.2 1/23 12w stereo/mono digital audio amplifier features z 16/18/20/24-bit input with i 2 s, left-alignment and right-alignment data format z psnr & dr(a-weighting) loudspeaker: 98db (psnr), 106db (dr) @24v z multiple sampling frequencies (fs) 32khz / 44.1khz / 48khz and 64khz / 88.2khz / 96khz and 128khz/176.4khz/192khz z system clock = 64x, 128x, 256x, 384x, 512x, 768x, 1024x fs 256x~1024x fs for 32khz / 44.1khz / 48khz 128x~512x fs for 64khz / 88.2khz / 96khz 64x~256x fs for 128kh z/176.4khz/192khz z supply voltage 3.3v for digital circuit 12v~24v for loudspeaker driver z loudspeaker output power for 24v 2 10w into 8 ? @0.19% thd+n for stereo 1 20w into 4 ? @0.18% thd+n for mono z loudspeaker output power for 24v with proper cooling method 2 26w into 8 ? @1% thd+n for stereo 1 53w into 4 ? @1% thd+n for mono z anti-pop design z over-temperature protection z internal pll z under-voltage shutdown z over-current protection z i 2 c control interface applications z cd and dvd z tv audio z car audio z boom-box z mp3 docking systems z powered speaker z wireless audio z usb speaker description this is a stereo (8 )/mono (4 ) fully digital audio amplifier with output power which can drive up to 2x12w for stereo or 1x24w for mono at 24v supply voltage, no external heat-sink or fan is requirement. using i 2 c digital control interface, AD82581B provides input format selection, mute and volume control function. protection circuits are provided to protect AD82581B damage while connection error. ordering information product number package comments AD82581B-leg 7x7 48l e-lqfp pb-free marking information line 1 logo line 2 product no line 3 tracking code line 4 date code
esmt preliminary AD82581B elite semiconductor memory technology inc. publication date: dec. 2008 revision: 0.2 2/23 pin assignment mclk clk_out dvdd dgnd def sdata mono lrcin n.c. n.c. sda scl sa1 sa0 error pd vddra ra gndr rb lb vddrb vddlb vddla la gndl pll bclk reset 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 n.c. n.c. dvdd dgnd n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. pin description pin name type description characteristics 1 n.c. 2 n.c. 3 pll i pll enable, low active schmitt trigger ttl input buffer 4 mclk i master clock input schmitt trigger ttl input buffer 5 clk_out o clock output from pll ttl output buffer 6 dgnd p digital ground 7 n.c. 8 dvdd p digital power 9 def i default volume setting schmitt trigger ttl input buffer 10 n.c. 11 n.c. 12 sdata i serial audio data input schmitt trigger ttl input buffer 13 n.c 14 mono i mono mode enable, high active schmitt trigger ttl input buffer 15 lrcin i left/right clock input (fs) schmitt trigger ttl input buffer 16 bclk i bit clock input (64fs) schmitt trigger ttl input buffer 17 pd i power down, low active schmitt trigger ttl input buffer
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